1. Field of the Invention
Embodiments of the present invention generally relate to semiconductor manufacturing. More specifically, embodiments of the present invention relate to a method and a system that automatically processes a pattern-clip-based manufacturing hotspot to determine both correction guidance descriptions for correcting the manufacturing hotspot and qualified ranges for the pattern clip to remain a manufacturing hotspot.
2. Related Art
Advances in IC manufacturing technology have enabled minimum feature sizes on IC chips to continuously decrease. In fact, the current minimum feature size is smaller than the wavelengths of light used in conventional optical imaging systems. Accordingly, it is becoming increasingly difficult to achieve reasonable fidelity, which is often expressed in resolution and depth of focus, between a designed layout and the shapes of actual fabricated circuit elements. Existing reticle enhancement technologies (RETs), such as optical proximity correction (OPC), phase-shifting masks (PSMs), and sub-resolution assist features (SRAFs), are becoming inadequate to solve fabrication issues on the nanometer scale.
Manufacturability-aware physical design, which takes into account both yield and reliability during the physical-design process, is becoming increasingly important in bridging the gap between design and manufacturing for nanometer-scale fabrication processes. Many yield and reliability issues can be attributed to certain layout configurations, referred to as “manufacturing hotspots” (also referred to as “process hotspot” or simply “hotspots”), which are susceptible to manufacturing process issues, such as stress and lithographic process fluctuations. For example, an increasing number of lithography-related manufacturing hotspots caused by increasing design complexity have become one of the main yield limiters of sub-65 nm IC designs. It is therefore desirable to identify and remove these process-related yield limiters from IC designs before design tapeout and replace them with more yield-friendly layout configurations.
Unfortunately, automatic techniques for modifying a layout to resolve the identified manufacturing hotspots are typically not available to the designers. Note that while manufacturers can routinely publish new “pattern clips” (clips of the layout which are associated with manufacturing hotspots) to make them available to designers, a pattern clip itself is not sufficient for designers to make correction decisions for the associated hotspot. This is because each hotspot is caused by the proximity effect associated with the entire pattern clip, and the hotspot configuration does not indicate which of the constituent geometries need to be altered to remove or reduce the severity of the hotspot.
Furthermore, note that often similar pattern clips provided by manufacturers constitute a hotspot range, within which a particular type of hotspot is considered “valid.” However, automatic techniques for determining a valid hotspot range (or ranges) based on a given pattern clip are also not available to the designers. Without such automatic techniques, processing a large number of manufacturer-provided pattern clips becomes extremely time consuming and redundant.
Hence, what is needed is a method and a system that can automatically process pattern-clip-based manufacturing hotspots without the above-described problems.